1 2 3 4 A B C D E ZZZ ZZZ ZZZ1 ZZZ1 ZZZ2 ZZZ2 ZZZ3 ZZZ3 PCB PCB LA5081P LA5081P DAZ DAZ LS5081P LS5081P DAZ DAZ LS5082P LS5082P DAZ DAZ KIWA5A6 Schematics Document Mobile Penryn uFCPGA with Intel CantigaGMPMICH9M core logic REV10 Security Classification Security Classification Security Classification Issued Date Issued Date Issued Date 20090423 20090423 20090423 Compal Secret Data Compal Secret Data Compal Secret Data Deciphered Date Deciphered Date Deciphered Date A B C D THIS SHEET OF ENGINEER......
A
B
C
D
E
ZZZ
ZZZ1
ZZZ2
ZZZ3
1
1
PCB
LA-5081P
DAZ@
LS-5081P
DAZ@
LS-5082P
DAZ@
2
KIWA5/A6
Schematics Document
Mobile Penryn uFCPGA with Intel
Cantiga_GM/PM+ICH9-M core logic
REV:1.0
2
3
3
4
4
Security Classification
Issued Date
Compal Secret Data
2009/04/23
Deciphered Date
Compal Electronics, Inc.
2010/05
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Cover Sheet
Size
B
Document Number
KIWAX_LA-5081P
Sheet
E
Rev
1.0
1
of
51
Date: Tuesday, April 28, 2009
A
B
C
D
E
Compal confidential
File Name :
ZZZ
POWER Board
PCB KIWA5 LA-5081P LS-5081P/5082P
CAP SENSE LEDs Board
1
VRAM
64*16
DDRII
page20,21
Mobile Penryn
uFCPGA-478 CPU
PCI-E X16
page5,6,7
H_A#(3..35)
H_D#(0..63)
1
NV10M-GS
40nm
page16,17,18,19
HDMI
CONN
page23
Clock Gen.
SLG8SP556VTR
ICS9LPRS387AKLFT
page22
FSB
667/800/1066MHz
Parade 8101T
ASM 1442T
PCI-E
page23
Intel Cantiga GMCH
PCBGA 1329
LVDS I/F
page 8,9,10,11,12,13
DDR3 -800
DDR3-1066
Dual Channel
DDR3-SO-DIMM X2
BANK 0, 1, 2, 3
page 14,15
CRT & TV OUT
page25
2
LVDS
Connector
PCI Express
Mini card Slot
page30
1
2
page24
DMI
C-Line
AMP&Audio Jack
AZALIA
page35
6*PCI-E BUS
USB 2.0 BUS
Intel ICH9-M
mBGA-676
page27,28,29,30
12*USB2.0
Audio Codec
CX20561
4*SATA serial
page34
Key component
Manufacturer
Compal P/N
R1 Desc
New Card
BCM5906
10/100/LAN
3
page30
Card Reader
page31
CMOS Camera
LPC BUS
page39
RTS 5159
page37
Northbridge
Intel / Cantiga PM45
SA00002JJM0
S IC AC82PM45 QV11 A1 FCBGA 1329 PM C38
3
BlueTooth Conn
page39
RJ45 CONN
page32
Card reader(XD/SD
MMC/MS/MS-Pro
HD SD)
page37
EC
ENE KB926
page36
Intel / Cantiga GM 45
SA00002JTD0
S IC AC82GM45 SLB94 B3 FCBGA1329 GM C38!
SouthBridge
Intel / ICH9M
SA00002JH90
S IC AF82801IBM SLB8Q A3 676P ICH9M C38! (MP)
VGA Chip
Nvidia / N10M
SA00002V810
S IC N10M-GE1-S-U2(H) BGA 533P C38
USB conn X3
page39
Int.KBD
Touch Pad
page39
page38
BIOS
page39
SATA HDD
Connector
page33
SATA CDROM
Connector
page33
VRAM
DDR2/512MB
SA00002MF00 (14")
S IC D2 64M16/500 HYB18T1G161C2F-20
SA00002UH00 (15.6")
S IC D2 64M16/500 H5PS1G63EFR-20L FBGA84
4
4
Security Classification
Issued Date
2009/04/23
Compal Secret Data
Deciphered Date
2010/05
Title
Compal Electronics, Inc.
MB Block Diagram
KIWAX_LA-5081P
Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Size Document Number
Custom
Date:
Rev
1.0
2
of
51
Tuesday, April 28, 2009
A
B
C
D
E
DDR3 Voltage Rails
power
plane
+5VALW
B+
1
+1.5V
+5VS
+3VS
+1.5VS
+0.75VS
+VCCP
+CPU_CORE
+VGA_CORE
+1.8VS
1
+3VALW
State
S0
S1
S3
S5 S4/AC
2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
X
X
X
X
CLK
GEN
CAP
Mini
Mini
THERMAL
SENSOR
(VGA)
THERMAL
SENSOR
(CPU)
2
X
X
X
SERIAL
EEPROM
NEW
CARD
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
X
X
X
SMBUS, SPI and I2C Control Table
SOURCE HDMI
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
ICH_SMBCLK
ICH_SMBDAT
LVDS_SCL
LVDS_SDA
GMCH_CRT_CLK
GMCH_CRT_DAT
HDMICLK_NB
HDMIDAT_NB
VGA_DDCCLK
VGA_DDCDATA
VGA_LVDS_SCL
VGA_LVDS_DAT
VGA_HDMI_SCL
VGA_HDMI_DAT
(55nm)
HDCP_SMB_CK1
HDCP_SMB_DA1
IFPC_AUX
IFPC_AUX_N
(40nm)
4
LVDS
CRT
HDCP
sensor CARD1 CARD2
BATT
KB926
KB926
X X X X
X X X X
X X X X
X
V
X X
X
V
X
X
X
X
X
V
V
X
V
X
X
X
X
X
X X X
X X X
X
V V
X X X
X
X
X
X
X
X
X
X
X
X
X
X
X X X
V
X
V
X X X
V
X
V V
X X
X X X X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
X
X
X
X
X
X
X
4
3
ICH9
3
Cantiga
Cantiga
Cantiga
N10M
N10M
N10M
N10M
V
X X X
X X X
V
V
X X X
X X X X
X X X
X X X
X X X
V
X X
X X X X X
X X X X X
X X X X X
X X X X X
Security Classification
Issued Date
N10M
FSEL#SPICS#
FRD#SPI_SO
SPI_CLK
FWR#SPI_SI
KB926
X
Compal Secret Data
2009/04/23
Deciphered Date
2010/05
Title
Size
B
Date:
Compal Electronics, Inc.
MB Notes List
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
KIWAX_LA-5081P
Tuesday, April 28, 2009
E
Rev
1.0
3
of
51
Sheet
A
B
C
D
E
VGA and DDR2 Voltage Rails
(N10M)
EDP at Tj = 97C*
Power Supply Rail
(V)
NVVDD
FB_DLLAVDD
Variable
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.8
1.8
1.8
1.8
1.8
1.8
1.8
3.3
3.3
3.3
3.3
3.3
3.3
3.3
NB10M-GS
GDDR3
11.22A
25mA
10mA
385mA
385mA
385mA
385mA
1550mA
165mA
55mA
25mA
50mA
3.425A
2.24A
50mA
50mA
100mA
160mA
160mA
2.76A
110mA
125mA
110mA
10mA
10mA
80mA
0.445A
2.17A
1.65A
DDR2
10.87A
N10M-GE1-S
GDDR3
13.56A
25mA
10mA
180mA
180mA
180mA
180mA
1550mA
65mA
30mA
10mA
25mA
2.435A
2.24A
50mA
50mA
75mA
80mA
80mA
2.575A
110mA
125mA
110mA
10mA
10mA
80mA
0.445A
2.085A
2
1
DDR2
13.47A
power
plane
1
FB_PLLAVDD
+3VS
+VGA_CORE
+1.1VS
+1.8VS
IFPC_IOVDD
IFPD_IOVDD
IFPE_IOVDD
IFPF_IOVDD
PEX_IOVDD/Q
PEX_PLLVDD
PLLVDD
SP_PLLVDD
VID_PLLVDD
TOTAL
FBVDD/Q
State
1.75A
S0
S1
S3
2
O
O
IFPA_IOVDD
IFPB_IOVDD
IFPAB_PLLVDD
IFPCD_PLLVDD
IFPEF_PLLVDD
TOTAL
DACA_VDD
DACB_VDD
DACC_VDD
MIOA_VDDQ
MIOB_VDDQ
VDD33
TOTAL
X
X
X
X
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery
don't exist
POWER SQUENCE
The ramp time for any rail must be more than 40us
3
3
(+3VS)
VDD33
PEX_VDD can ramp up any time
(1.1VS) PEX_VDD
tNVVDD>=0
(+VGA_CORE)
NVVDD
tNV-FB
tFBVDDQ>=0
4
(1.8VS)
FBVDDQ
4
Security Classification
Issued Date
2009/04/23
Compal Secret Data
Deciphered Date
2010/05
Title
Size
B
Date:
Compal Electronics, Inc.
VGA Notes List
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
KIWA5/6 LA-5081P
Tuesday, April 28, 2009
E
Rev
1.0
of
51
Sheet
4
5
4
3
2
1
XDP Reserve
XDP_DBRESET#
R43
+3VS
1
2
@
1K_0402_5%
+VCCP
XDP_TDI
D
R11
R14
R12
1
1
1
@
2
2
2
54.9_0402_1%
54.9_0402_1%
54.9_0402_1%
D
XDP_TMS
(8)
H_A#[3..16]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
CONN@
JCPUA
+VCCP
XDP_TDO
CONTROL
(8)
(8)
(8)
(8)
(8)
(8)
(8)
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#[17..35]
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
1
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR0#
H_IERR#
H_INIT#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_ADS#
H_BNR#
H_BPRI#
(8)
(8)
(8)
2
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
H_HIT#
(8)
H_HITM# (8)
0.1U_0402_16V4Z
C
2
1
H_THERMDA
1
XDP/ITP SIGNALS
ADDR GROUP_0
H_DEFER# (8)
H_DRDY# (8)
H_DBSY# (8)
H_BR0#
(8)
(27)
R83
56_0402_5%
XDP_TRST#
R16
R15
1
1
2
2
54.9_0402_1%
54.9_0402_1%
H_INIT#
H_LOCK# (8)
H_RESET# (8)
H_RS#0
(8)
H_RS#1
(8)
H_RS#2
(8)
H_TRDY# (8)
2
XDP_TCK
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
+3VS
EMC1402
ADT7421ARMZ
SA00001Z700
SA00001UN00
+3VS
R95
10K_0402_5%
1
C89
U5
ADDR GROUP_1
C
VDD
DP
DN
THERM#
SMCLK
SMDATA
ALERT#
GND
8
7
6
5
EC_SMB_CK2
EC_SMB_DA2
EC_SMB_CK2 (16,36)
EC_SMB_DA2 (16,36)
C95
2
3
4
1
2
2200p change to
1000p for ADT7421
XDP_DBRESET# (28)
H_THERMDC
2200P_0402_50V7K
THERM#
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
D21
A24
B25
C7
2
R84
H_PROCHOT#
H_THERMDA
H_THERMDC
H_THERMTRIP#
1
68_0402_5%
+3VS
+VCCP
H_PROCHOT#
R94
1
2
10K_0402_5%
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100
(8)
H_ADSTB#1
(27) H_A20M#
(27) H_FERR#
(27) H_IGNNE#
(27)
(27)
(27)
(27)
H_STPCLK#
H_INTR
H_NMI
H_SMI#
A20M#
FERR#
IGNNE#
ICH
ICH
H_THERMTRIP# (8,27)
H_STPCLK#
D5
H_INTR
C6
H_NMI
B4
H_SMI#
A3
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
H CLK
BCLK[0]
BCLK[1]
A22
A21
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK (22)
CLK_CPU_BCLK# (22)
G990
APL5605
RT9027
SA00002GW00
SA00001Z900
SA000022J00
+5VS
C594
1
FAN1 Conn
+5VS
B
RESERVED
RSVD pins on the CPU
should be left as NO
CONNECT
M4
N5
T2
V3
B2
D2
D22
D3
F6
H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
1
10U_0805_10V4Z
2
B
FAN solution RC (R=1Kohm,C=0.1uF)
(36)
EN_FAN1
EN_FAN1
U24
D17
@
1SS355TE-17_SOD323-2
1
2
R667
1K_0402_5%
1
<BOM Structure>
+VCC_FAN1
EN_FAN1_R
1
2
3
4
VEN
VIN
VO
VSET
GND
GND
GND
GND
8
7
6
5
@
1
D16
2
BAS16_SOT23-3
2
G990P11U_SO8
C810
0.1U_0402_16V4Z
C595
1U_0603_10V4Z
1
2
+3VS
C597
0.1U_0402_16V4Z
1
2
Penryn
2
1
R469
10K_0402_5%
40mil
2
+VCC_FAN1
(36) FAN_SPEED1
JP13
1
2
3
4
5
1
1
2
3
GND
GND
E&T_3801-F03N-01R
A
C596
1000P_0402_50V7K
A
2
Security Classification
Issued Date
Compal Secret Data
2009/04/23
Deciphered Date
2010/05
Title
Size
B
Date:
Compal Electronics, Inc.
Penryn (1/3)
Document Number
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
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